Independent Verification Engineer

Mike Kentley

I make things. Specifically, I make verification work on silicon that can’t fail.

Reticle-scale AI accelerators. Spaceflight electronics. Pacemakers. The hard verification problems other people walk away from.

Email Mike → LinkedIn

§ 01 / WHAT I DO

Pulled in when verification is in trouble.

Independent verification engineer and consultant, working through High Desert Design Center (founded 1998).

Pulled in when a verification effort is in trouble, when a team is scoping a program and wants a senior set of eyes, or when a flagship part needs a verification lead who has shipped reticle-scale silicon before.

§ 02 / RECENT & CURRENT WORK

What I’ve shipped.

AI Accelerators

Groq LPU — verification engineer across three revs. V2 in production datacenter compute. V3 became the NVIDIA Groq LPX. Earlier: SambaNova (PCIe Gen4 subsystem), Luminous Computing (PCIe Gen5 bridge SoC, architect & RTL).

Spaceflight Electronics
NASA / JPL

Currently: a JPL flight program. Past: Mars Sample Return (SpaceWire validation), EMIT instrument on the ISS (image-processing FPGA blocks).

Datacenter & High-Speed I/O

Currently: 800G networking SoC. Past: AWS Annapurna (FPGA security subsystem, three granted US patents). Cornelis Networks (chip secure boot, efuse, debug). PCIe Gen3–Gen6, CXL, USB 2/3.x/4.

High-Reliability Medical

Medtronic — UVM verification components for next-generation pacemakers, including high-voltage pacing IC respin.

§ 03 / CAPABILITIES

The toolkit.

Methodologies

UVM · SystemVerilog · gate-level simulation · formal property verification · emulation · SystemC HLS

Protocols

PCIe Gen3–Gen6 · CXL · USB 2 / 3.x / 4 · SpaceWire · AXI · AHB · APB · JTAG · I2C · SPI · DDR5

Tools

Synopsys VCS / Verdi · Cadence Xcelium and Stratus HLS · Siemens Questa · Xilinx / Altera / Lattice FPGA flows

Adjacent

Front-end design · board design · firmware bring-up · full-custom memory/logic · ARM

§ 04 / PATENTS & TEACHING

On the public record.

U.S. 10,938,782 Secure Hardware Signal Filtering 2021
U.S. 10,810,336 Traffic Management on an Interconnect 2020
U.S. 10,430,225 Traffic Management on an Interconnect 2019
U.S. 8,862,803 Mediating Communication of a USB Device 2012

Author, Mindshare USB 2.0 Embedded eLearning Course (2009). Trainer, Mindshare Inc. — delivered on-site PCIe and USB training to Fortune 100 design and verification teams.

§ 05 / CONTACT

Get in touch.

mike@mikekentley.com

(541) 948-3810

linkedin.com/in/mikekentley

Bend, Oregon · United States